CVE-2026-53354 - Vulnerability Details

Vendors	Products
Linux	Linux Kernel

Link	Providers
https://git.kernel.org/stable/c/1268c64e2bcb6e968152990e87bd10c440fcc9c0
https://git.kernel.org/stable/c/1b47b1e1d8675fdf5f6e11e7fa19c704d8c6f5cd
https://git.kernel.org/stable/c/4e7c80742e6dada9f8b9ad63f3a49c03af07ecb8
https://git.kernel.org/stable/c/7c3ad9365079e716b57d2363d3081ee7680cc18e
https://git.kernel.org/stable/c/8364384ae82fbffdf8968abaac3455ed854da18d
https://git.kernel.org/stable/c/925058203229403008d77a52b1e63e2ae5f4a3cf
https://git.kernel.org/stable/c/cfd391e74134db664feb499d43af286380b10ba8
https://git.kernel.org/stable/c/d4fd4282204044fdedd1e42abbe70a9206f74ec0
https://git.kernel.org/stable/c/e717a4d08779f1a28d6e0275e75040b12c33c753

Type	Values Removed	Values Added
Description		In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number.
Title		arm64: errata: Mitigate TLBI errata on various Arm CPUs
First Time appeared		Linux Linux linux Kernel
CPEs		cpe:2.3:o:linux:linux_kernel::::::::
Vendors & Products		Linux Linux linux Kernel
References		https://git.kernel.org/stable/c/1268c64e2bcb6e968152990e87bd10c440fcc9c0 https://git.kernel.org/stable/c/1b47b1e1d8675fdf5f6e11e7fa19c704d8c6f5cd https://git.kernel.org/stable/c/4e7c80742e6dada9f8b9ad63f3a49c03af07ecb8 https://git.kernel.org/stable/c/7c3ad9365079e716b57d2363d3081ee7680cc18e https://git.kernel.org/stable/c/8364384ae82fbffdf8968abaac3455ed854da18d https://git.kernel.org/stable/c/925058203229403008d77a52b1e63e2ae5f4a3cf https://git.kernel.org/stable/c/cfd391e74134db664feb499d43af286380b10ba8 https://git.kernel.org/stable/c/d4fd4282204044fdedd1e42abbe70a9206f74ec0 https://git.kernel.org/stable/c/e717a4d08779f1a28d6e0275e75040b12c33c753

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TLB entries are removed\ncorrectly.\n\nThis issue has been assigned CVE ID CVE-2025-10263.\n\nTo mitigate this issue, Arm recommends that software follows any\naffected TLBI;DSB sequence with an additional TLBI;DSB, which will\nensure that all memory write effects affected by the first TLBI have\nbeen globally observed. The additional TLBI can use any operation that\nis broadcast to affected CPUs, and the additional DSB can use any option\nthat is sufficient to complete the additional TLBI.\n\nThe ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate\nthe issue. Enable this workaround for affected CPUs, and update the\nsilicon errata documentation accordingly.\n\nNote that due to the manner in which Arm develops IP and tracks errata,\nsome CPUs share a common erratum number."}], "affected": [{"product": "Linux", "vendor": "Linux", "defaultStatus": "unaffected", "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git", "programFiles": ["Documentation/arch/arm64/silicon-errata.rst", "arch/arm64/Kconfig", "arch/arm64/kernel/cpu_errata.c"], "versions": [{"version": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "lessThan": "925058203229403008d77a52b1e63e2ae5f4a3cf", "status": "affected", "versionType": "git"}, {"version": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "lessThan": "8364384ae82fbffdf8968abaac3455ed854da18d", "status": "affected", "versionType": "git"}, {"version": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "lessThan": "7c3ad9365079e716b57d2363d3081ee7680cc18e", "status": "affected", "versionType": "git"}, {"version": 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"versionType": "semver"}, {"version": "0", "lessThan": "5.15.210", "status": "affected", "versionType": "semver"}, {"version": "0", "lessThan": "6.1.176", "status": "affected", "versionType": "semver"}, {"version": "0", "lessThan": "6.6.143", "status": "affected", "versionType": "semver"}, {"version": "0", "lessThan": "6.12.94", "status": "affected", "versionType": "semver"}, {"version": "0", "lessThan": "6.18.36", "status": "affected", "versionType": "semver"}, {"version": "0", "lessThan": "7.0.13", "status": "affected", "versionType": "semver"}, {"version": "0", "lessThan": "7.1.1", "status": "affected", "versionType": "semver"}]}, {"product": "Linux", "vendor": "Linux", "defaultStatus": "affected", "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git", "programFiles": ["Documentation/arch/arm64/silicon-errata.rst", "arch/arm64/Kconfig", "arch/arm64/kernel/cpu_errata.c"], "versions": [{"version": "5.10.259", "lessThanOrEqual": "5.10.*", "status": "unaffected", "versionType": "semver"}, {"version": "5.15.210", "lessThanOrEqual": "5.15.*", "status": "unaffected", "versionType": "semver"}, {"version": "6.1.176", "lessThanOrEqual": "6.1.*", "status": "unaffected", "versionType": "semver"}, {"version": "6.6.143", "lessThanOrEqual": "6.6.*", "status": "unaffected", "versionType": "semver"}, {"version": "6.12.94", "lessThanOrEqual": "6.12.*", "status": "unaffected", "versionType": "semver"}, {"version": "6.18.36", "lessThanOrEqual": "6.18.*", "status": "unaffected", "versionType": "semver"}, {"version": "7.0.13", "lessThanOrEqual": "7.0.*", "status": "unaffected", "versionType": "semver"}, {"version": "7.1.1", "lessThanOrEqual": "7.1.*", "status": "unaffected", "versionType": "semver"}, {"version": "7.2-rc1", "lessThanOrEqual": "*", "status": "unaffected", "versionType": "original_commit_for_fix"}]}], "cpeApplicability": [{"nodes": [{"operator": "OR", "negate": false, "cpeMatch": [{"vulnerable": true, "criteria": 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"7.2-rc1"}]}]}], "references": [{"url": "https://git.kernel.org/stable/c/925058203229403008d77a52b1e63e2ae5f4a3cf"}, {"url": "https://git.kernel.org/stable/c/8364384ae82fbffdf8968abaac3455ed854da18d"}, {"url": "https://git.kernel.org/stable/c/7c3ad9365079e716b57d2363d3081ee7680cc18e"}, {"url": "https://git.kernel.org/stable/c/e717a4d08779f1a28d6e0275e75040b12c33c753"}, {"url": "https://git.kernel.org/stable/c/4e7c80742e6dada9f8b9ad63f3a49c03af07ecb8"}, {"url": "https://git.kernel.org/stable/c/d4fd4282204044fdedd1e42abbe70a9206f74ec0"}, {"url": "https://git.kernel.org/stable/c/1b47b1e1d8675fdf5f6e11e7fa19c704d8c6f5cd"}, {"url": "https://git.kernel.org/stable/c/1268c64e2bcb6e968152990e87bd10c440fcc9c0"}, {"url": "https://git.kernel.org/stable/c/cfd391e74134db664feb499d43af286380b10ba8"}], "title": "arm64: errata: Mitigate TLBI errata on various Arm CPUs", "x_generator": {"engine": "bippy-1.2.0"}}}}

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